I. Field
The present disclosure relates generally to electronics, and more specifically to graphics processors.
II. Background
Graphics processors are widely used to render 2-dimensional (2-D) and 3-dimensional (3-D) images for various applications such as video games, graphics, computer-aided design (CAD), simulation and visualization tools, imaging, etc. A graphics processor may perform computationally intensive processing on large amount of graphics data to render an image. For example, a 3-D image may be represented with many triangles (e.g., in the millions), and each triangle may be defined by three vertices. Each vertex may be associated with various attributes such as space coordinates, color values, and texture coordinates, and each attribute may have up to four components. The graphics processor may render each triangle by determining the values of the components of each picture element (pixel) within the triangle. The graphics operations and the large quantity of data may require high processing capability for acceptable performance.
In order to achieve higher processing throughput, a graphics processor may include multiple shader units and/or multiple arithmetic logic units (ALUs). Depending on the processor design, co-issue and/or dual-issue of instructions for the same thread of execution (or simply, thread) may be supported. Co-issue refers to execution of two instructions for the same thread in parallel by two processing units on the same clock cycle. Dual-issue refers to execution of two instructions for the same thread in a pipelined manner by two processing units. A combination of dual-issue and co-issue may also be supported.
Co-issue and dual-issue techniques are challenging to implement. A compiler would need to identify and address hardware restrictions, memory read/write conflicts, etc. Furthermore, co-issue may not be applicable for every type of instruction, and dual-issue may result in other limitations such as heavy usage of register file ports and data dependency. Co-issue and dual-issue typically complicate the design of the scheduler and may further result in wider instruction words.